This invention relates to a video signal processing circuit operative to reproduce still pictures from a color video signal.
The technical development is under way for upgrading the picture displayed on a color television receiver, VTR, video disc player, etc. for example, through the digital signal processing for the color television signal. The achievement of upgraded picture quality is a crucial technical theme especially for the color television receiver, and it is going to be attained by the developments of the comb filter circuit using a digital memory, the scanning line interpolation circuit, and the motion detecting circuit, as disclosed in JP-A No. 54-138325 (laid open on Oct. 26, 1979) and JP-A No. 61-15635 (laid open on Apr. 25, 1986). In another direction of digital processing, attempts have been made for the specific reproduction of pictures using a capacious memory. The specific reproduction is a function such as picture freezing and combined reproduction of a main and subordinate pictures (so-called "picture-in-picture" or "PinP"), and various methods have already been proposed.
For example, disclosed in JP-A No. 61-182283 (laid open on Sept. 17, 1985) is pertinent to picture freezing. This system will be briefed on the block diagram of FIG. 1A. In the figure, indicated by 201 is a field memory for storing a field of picture signal, 202 is a 1H memory for delaying the output signal of the field memory 201 by one scanning line, 203 is an adder for summing the input and output signals of the 1H memory 202, 204 is a coefficient multiplier which halves the output signal of the adder 203, 205 is a switch circuit for selecting one of output signals of the 1H memory 202 and coefficient multiplier 204, 206 is an input terminal for receiving the frame sync pulse signal FP shown in FIG. 1B, 207 is a switch for conducting the control signal to the switch circuit 205, and 208 is an output terminal for delivering the still picture signal.
In this conventional system, a field of picture signal is read out of the field memory 201 iteratively to display a still picture, i.e., frozen picture. In this case, if the switch 207 is turned off, causing the switch circuit 205 to be set to the a-position invariably, the output terminal 208 delivers the same signal for every field. Accordingly, by adjusting the read-out timing for the field memory 201, a non-interlaced scanning picture, e.g., a field-freeze picture having 262 scanning lines for each field can be displayed. If, on the other hand, the switch 207 is turned on, causing the switch circuit 205 to be controlled by the frame pulse FP supplied on the input, terminal 206, the switch circuit 205 is set to the a or b-position alternately in every second field. Consequently, the output terminal 208 delivers the signal of the field memory 201 in the a-position of the switch circuit 205 in the n-th field, and delivers the interpolated signal in the b-position of the switch circuit 205 produced by the filter circuit made up of the 1H memory 202, adder 203 and coefficient multiplier 204 in the (n+1)th field. Namely, the system provides a pseudo frame-freeze picture with a pseudo interlaced structure having 525 scanning lines.
The above conventional system allows the selection of field freeze and pseudo frame freeze depending on the nature of the picture signal stored in the field memory 201, whereby a still picture without quiver can be displayed. However, any of the field-freeze picture an pseudo frame-freeze picture is low in resolution, i.e., half as much scanning lines as the normally reproduced picture, and this is a problem from the viewpoint of upgrading the picture quality.
With the intention of improving the resolution, a complete frame of picture signal can be stored and read out iteratively to display a frame-freeze picture. However, it creates double images (quiver) at a moving portion of picture, and therefore upgrading of picture quality cannot be expected.
The following U.S. patent applications are cited as related applications:
(a) U.S. patent application Ser. No. 932,376, now U.S. Pat. No. 4,736,252 filed on Nov. 20, 1986, entitled "MOTION DETECTOR FOR CHROMINANCE SIGNAL IN TV RECEIVER"; PA0 (b) U.S. patent application Ser. No. 938,962, now U.S. Pat. No. 4,733,247 filed on Dec. 8, 1986, entitled "CONTOUR SIGNAL CORRECTION CIRCUIT FOR TELEVISION RECEIVER"; PA0 (c) U.S. patent application Ser. No. 36,431, now U.S. Pat. No. 4,733,247 filed on Apr. 9, 1987, entitled "VIDEO SIGNAL PROCESSING CIRCUIT OF MOTION-ADAPTIVE TYPE"; PA0 (d) U.S. patent application Ser. No. 63,477, filed on Jun. 18, 1987, entitled "DETECTION CIRCUIT FOR DETECTING STANDARD TELEVISION SIGNAL"; and PA0 (e) U.S. patent application Ser. No. 164,914 filed on Mar. 7, 1988, entitled "SIGNAL PROCESSING CIRCUIT USED IN TELEVISION RECEIVER FOR PROCESSING STANDARD AND NONSTANDARD TELEVISION SIGNALS" (based on Japanese Patent Application No. 62-51909, filed on Mar. 9, 1987).
Furthermore, U.S. Pat. No. 4,641,188 to Dischert discloses a receiver including a line store progressive scan processor for doubling the line rate of a video input signal for display.